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| ICS348 Quad PLL Field Programmable VersaClock Synthesizer Description The ICS348 field programmable clock synthesizer generates up to 9 high-quality, high-frequency clock outputs including multiple reference clocks from a low frequency crystal or clock input. The ICS348 has 4 independent on-chip PLLs and is designed to replace crystals and crystal oscillators in most electronic systems. Using ICS' VersaClock software to configure PLLs and outputs, the ICS348 contains a One-Time Programmable (OTP) ROM to allow field programmability. Programming features include eight selectable configuration registers, up to two sets of four low-skew outputs. Using Phase-Locked Loop (PLL) techniques, the device runs from a standard fundamental mode, inexpensive crystal, or clock. It can replace multiple crystals and oscillators, saving board space and cost. The ICS348 is also available in factory programmed custom versions for high-volume applications. TM Features * * * * * * * * * * * Packaged as 20-pin SSOP (QSOP) Eight addressable registers Replaces multiple crystals and oscillators Output frequencies up to 200 MHz at 3.3V Input crystal frequency of 5 to 27 MHz Input clock frequency of 2 to 50 MHz Up to nine reference outputs Up to two sets of four low-skew outputs Operating voltages of 3.3 V Advanced, low power CMOS process For one output clock, use the ICS341 (8-pin). For two output clocks, use the ICS342 (8-pin). For three output clocks, use the ICS343 (8-pin). For more than three outputs, use the ICS345 or ICS348. * Available in Pb (lead) free packaging Block Diagram V DD 3 S 2:S 0 3 O TP ROM w ith P LL V alues P LL1 CLK1 CLK2 P LL2 P LL3 C rystal or clock input X 1/IC LK C rystal O scillator X2 GND 2 P LL4 Divide Logic and Output Enable Control CLK3 CLK4 CLK5 CLK6 CLK7 CLK8 CLK9 E xternal capacitors are required w ith a crystal input. P D TS MDS 348 H Integrated Circuit Systems, Inc. 1 525 Race Street, San Jose, CA 95126 Revision 051705 tel (408) 297-1201 www.icst.com ICS348 Quad PLL Field Programmable VersaClock Synthesizer Pin Assignment X1/ICLK S0 S1 CLK9 VDD GND CLK1 CLK2 CLK3 CLK4 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 X2 VDD PDTS S2 VDD GND CLK5 CLK6 CLK7 CLK8 20-pin (150 mil) SSOP (QSOP) Pin Descriptions Pin Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 Pin Name X1 S0 S1 CLK9 VDD GND CLK1 CLK2 CLK3 CLK4 CLK8 CLK7 CLK6 CLK5 GND VDD S2 PDTS VDD X2 Pin Type XI Input Input Output Power Power Output Output Output Output Output Output Output Output Power Power Input Input Power XO Pin Description Crystal Input. Connect this pin to a crystal or external input clock. Select pin 0. Internal pull-up resistor. Select pin 1. Internal pull-up resistor. Output clock 9. Weak internal pull-down when tri-state. Connect to +3.3 V. Connect to ground. Output clock 1. Weak internal pull-down when tri-state. Output clock 2. Weak internal pull-down when tri-state. Output clock 3. Weak internal pull-down when tri-state. Output clock 4. Weak internal pull-down when tri-state. Output clock 8. Weak internal pull-down when tri-state. Output clock 7. Weak internal pull-down when tri-state. Output clock 6. Weak internal pull-down when tri-state. Output clock 5. Weak internal pull-down when tri-state. Connect to ground. Connect to +3.3 V. Select pin 2. Internal pull-up resistor. Power down tri-state. Powers down entire chip and tri-states clock outputs when low. Internal pull-up resistor. Connect to +3.3 V. Crystal Output. Connect this pin to a fundamental crystal. Float for clock input. MDS 348 H Integrated Circuit Systems, Inc. 2 525 Race Street, San Jose, CA 95126 Revision 051705 tel (408) 297-1201 www.icst.com ICS348 Quad PLL Field Programmable VersaClock Synthesizer External Components Series Termination Resistor Clock output traces over one inch should use series termination. To series terminate a 50 trace (a commonly used trace impedance), place a 33 resistor in series with the clock line, as close to the clock output pin as possible. The nominal impedance of the clock output is 20. spaces, instead they should be separated and away from other traces. 3) To minimize EMI, the 33 series termination resistor, if needed, should be placed close to the clock output. 4) An optimum layout is one with all components on the same side of the board, minimizing vias through other signal layers Decoupling Capacitors As with any high-performance mixed-signal IC, the ICS348 must be isolated from system power supply noise to perform optimally. Decoupling capacitors of 0.01F must be connected between each VDD and the PCB ground plane. ICS348 Configuration Capabilities The architecture of the ICS348 allows the user to easily configure the device to a wide range of output frequencies, for a given input reference frequency. The frequency multiplier PLL provides a high degree of precision. The M/N values (the multiplier/divide values available to generate the target VCO frequency) can be set within the range of M = 1 to 2048 and N = 1 to 1024. The ICS348 also provides separate output divide values, from 2 through 20, to allow the two output clock banks to support widely differing frequency values from the same PLL. Each output frequency can be represented as: OutputFreq REFFreq ------------------------------------OutputDivide ---M N Crystal Load Capacitors The device crystal connections should include pads for small capacitors from X1 to ground and from X2 to ground. These capacitors are used to adjust the stray capacitance of the board to match the nominally required crystal load capacitance. Because load capacitance can only be increased in this trimming process, it is important to keep stray capacitance to a minimum by using very short PCB traces (and no vias) been the crystal and device. Crystal capacitors must be connected from each of the pins X1 and X2 to ground. The value (in pF) of these crystal caps should equal (CL -6 pF)*2. In this equation, CL= crystal load capacitance in pF. Example: For a crystal with a 16 pF load capacitance, each crystal capacitor would be 20 pF [(16-6) x 2] = 20. = ICS VersaClock Software ICS applies years of PLL optimization experience into a user friendly software that accepts the user's target reference clock and output frequencies and generates the lowest jitter, lowest power configuration, with only a press of a button. The user does not need to have prior PLL experience or determine the optimal VCO frequency to support multiple output frequencies. VersaClock software quickly evaluates accessible VCO frequencies with available output divide values and provides an easy to understand, bar code rating for the target output frequencies. The user may evaluate output accuracy, performance trade-off scenarios in seconds. PCB Layout Recommendations For optimum device performance and lowest output phase noise, the following guidelines should be observed. 1) Each 0.01F decoupling capacitor should be mounted on the component side of the board as close to the VDD pin as possible. No vias should be used between decoupling capacitor and VDD pin. The PCB trace to VDD pin should be kept as short as possible, as should the PCB trace to the ground via. 2) The external crystal should be mounted just next to the device with short traces. The X1 and X2 traces should not be routed next to each other with minimum MDS 348 H Integrated Circuit Systems, Inc. 3 525 Race Street, San Jose, CA 95126 Revision 051705 tel (408) 297-1201 www.icst.com ICS348 Quad PLL Field Programmable VersaClock Synthesizer Absolute Maximum Ratings Stresses above the ratings listed below can cause permanent damage to the ICS348. These ratings, which are standard values for ICS commercially rated parts, are stress ratings only. Functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods can affect product reliability. Electrical parameters are guaranteed only over the recommended operating temperature range. Parameter Supply Voltage, VDD Inputs Clock Outputs Storage Temperature Soldering Temperature Junction Temperature Condition Referenced to GND Referenced to GND Referenced to GND Max 10 seconds Min. -0.5 -0.5 -65 Typ. Max. 7 VDD+0.5 VDD+0.5 150 260 125 Units V V V C C C Recommended Operation Conditions Parameter Ambient Operating Temperature (ICS348RP) Ambient Operating Temperature (ICS348RIP) Power Supply Voltage (measured in respect to GND) Power Supply Ramp Time Min. 0 -40 +3.15 Typ. Max. +70 +85 Units C C V ms +3.3 +3.45 4 MDS 348 H Integrated Circuit Systems, Inc. 4 525 Race Street, San Jose, CA 95126 Revision 051705 tel (408) 297-1201 www.icst.com ICS348 Quad PLL Field Programmable VersaClock Synthesizer DC Electrical Characteristics Unless stated otherwise, VDD = 3.3 V 5%, Ambient Temperature -40 to +85C Parameter Operating Voltage Symbol VDD Conditions Configuration Dependent - See VersaClockTM Estimates Min. 3.15 Typ. Max. 3.45 Units V mA Operating Supply Current Input High Voltage IDD Nine 33.3333 MHz outs, PDTS = 1, no load, Note 1 PDTS = 0, no load S2:S0 S2:S0 VDD-0.5 2 23 mA 20 0.4 0.4 Input High Voltage Input Low Voltage Input High Voltage, PDTS Input Low Voltage, PDTS Input High Voltage Input Low Voltage Output High Voltage (CMOS High) Output High Voltage Output Low Voltage Short Circuit Current Nominal Output Impedance Internal pull-up resistor Internal pull-down resistor Input Capacitance VIH VIL VIH VIL VIH VIL VOH VOH VOL IOS ZO RPUS RPD CIN A V V V V V VDD/2-1 V V V 0.4 V mA k k pF ICLK ICLK IOH = -4 mA IOH = -12 mA IOL = 12mA VDD/2+1 VDD-0.4 2.4 70 20 S2:S0, PDTS CLK outputs Inputs 250 525 4 Note 1: Example with 25 MHz crystal input with nine outputs of 33.3 MHz, no load, and VDD = 3.3 V. MDS 348 H Integrated Circuit Systems, Inc. 5 525 Race Street, San Jose, CA 95126 Revision 051705 tel (408) 297-1201 www.icst.com ICS348 Quad PLL Field Programmable VersaClock Synthesizer AC Electrical Characteristics Unless stated otherwise, VDD = 3.3 V 5%, Ambient Temperature -40 to +85 C Parameter Input Frequency Output Frequency Output Rise Time Output Fall Time Duty Cycle Output Frequency Synthesis Error Power-up time Symbol FIN Conditions Fundamental Crystal Input Clock VDD=3.3 V Min. 5 2 0.25 Typ. Max. Units 27 50 200 MHz MHz MHz ns ns 60 % ppm 10 2 ms ms ps ps 250 ps tOR tOF 20% to 80%, Note 1 80% to 20%, Note 1 Note 2 Configuration Dependent PLL lock-time from power-up, Note 3 PDTS goes high until stable CLK output, Note 3 40 1 1 49-51 TBD 3 0.2 50 +200 -250 One Sigma Clock Period Jitter Maximum Absolute Jitter Pin-to-Pin Skew Note 1: Measured with 15 pF load. tja Configuration Dependent Deviation from Mean. Configuration Dependent Low Skew Outputs Note 2: Duty Cycle is configuration dependent. Most configurations are minimum 45% and maximum 55%. Note 3: ICS test mode output occurs for first 170 clock cycles on CLK7 for each PLL powered up. PDTS transition high on select address change. Thermal Characteristics Parameter Thermal Resistance Junction to Ambient Symbol JA JA JA JC Conditions Still air 1 m/s air flow 3 m/s air flow Min. Typ. 135 93 78 60 Max. Units C/W C/W C/W C/W Thermal Resistance Junction to Case MDS 348 H Integrated Circuit Systems, Inc. 6 525 Race Street, San Jose, CA 95126 Revision 051705 tel (408) 297-1201 www.icst.com ICS348 Quad PLL Field Programmable VersaClock Synthesizer Package Outline and Package Dimensions (20-pin SSOP, 150 Mil. Wide Body) Package dimensions are kept current with JEDEC Publication No. 95 20 Millimeters Symbol Min Max Inches Min Max E1 INDEX AREA E 12 D A2 A1 A A A1 A2 b c D E E1 e L aaa 1.35 1.75 0.10 0.25 -1.50 0.20 0.30 0.18 0.25 8.55 8.75 5.80 6.20 3.80 4.00 .635 Basic 0.40 1.27 0 8 -0.10 0.053 0.069 0.004 0.010 -0.059 0.008 0.012 0.007 0.010 0.337 0.344 0.228 0.244 0.150 0.157 .025 Basic 0.016 0.050 0 8 -0.004 c -Ce b SEATING PLANE L aaa C Ordering Information Part / Order Number ICS348RP ICS348RPT ICS348RIP ICS348RIPT ICS348RPLF ICS348RPLFT ICS348RIPLF ICS348RIPLFT Marking ICS348RP ICS348RP ICS348RIP ICS348RIP ICS348RLF ICS348RLF ICS348RIPLF ICS348RIPLF Shipping Packaging Tubes Tape and Reel Tubes Tape and Reel Tubes Tape and Reel Tubes Tape and Reel Package 20-pin SSOP 20-pin SSOP 20-pin SSOP 20-pin SSOP 20-pin SSOP 20-pin SSOP 20-pin SSOP 20-pin SSOP Temperature 0 to +70 C 0 to +70 C -40 to +85 C -40 to +85 C 0 to +70 C 0 to +70 C -40 to +85 C -40 to +85 C Parts that are ordered with a "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant. While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems (ICS) assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments. MDS 348 H Integrated Circuit Systems, Inc. 7 525 Race Street, San Jose, CA 95126 Revision 051705 tel (408) 297-1201 www.icst.com |
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